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  • Intel's Nehalem levels playing field with AMD

    At its recent Developer Forum, Intel laid out the last remaining secrets of Nehalem, a remade x86 platform built around a highly integrated Core 2 microprocessor with on-board memory and point-to-point bus controllers. I fairly raved about it, a fact that caught some who view me as an AMD die-hard by surprise.
    Being a chiphead, but well shy of a chipmaker, I needed an independent perspective on Intel's first substantial effort to carry the x86 platform beyond the standards and boundaries set by IBM's PC-AT. Intel finally dumped the shared bus. That doesn't set a new high for the industry, but it certainly redefines Intel and lays down a new road for Intel-based servers and workstations.
    While I had a head full of Nehalem facts, what I lacked was balance. Intel's IDF sessions on Nehalem compared the platform and CPU architecture only to Intel's work to date which, while I wouldn't call it sub-par, had been out-engineered by AMD.
    For a valid contrast, I need to weigh Nehalem against AMD's own 45nm quad-core technology, dubbed Shanghai. That's a platform/architecture shoot-out for the ages, and I'm all over it. But since neither technology is shipping yet, all I can compare is detailed specs and higher-altitude rhetoric. The specs will take some digging. Today I'll tackle the rhetoric, the rationale behind Intel's design decisions, and the packaging of those decisions as competitive advantages. How much of what Intel's done with Nehalem is actually unique, and will IT feel the difference?
    I brought a slate of questions to AMD and invited an expert in AMD server architecture and platforms, to address them. We covered an enormous amount of ground. The upshot is this: AMD celebrates Intel's validation of innovations that AMD designed into Opteron closer to the turn of the century. The x86-64 instruction set, non-uniform memory access (NUMA, which gives each processor socket its own RAM), Direct Connect (Intel calls its incarnation QuickPath) socket-to-socket bus, on-chip independent memory and bus controllers, independent power control for each core, internal power and thermal management, multiple processors on a single contiguous mask, dedicated Level 2 cache for each core, and shorter pipelines are features that AMD claims as firsts in the x86 domain. Intel once blew off each of these features as irrelevant. Now Nehalem and related platforms adopt all of them.
    This is a good thing. When Nehalem goes up against Shanghai, it's apples-to-apples on platforms, or at least it will be treated as such. Even though the savviest server buyers could grasp the scalability advantages of AMD's NUMA and Direct Connect over Intel's shared bus, AMD won't be able to put across subtler differences between AMD's and Intel's implementation of the same ideas. When platform differences get small enough to require debate among gearheads, there is little chance of translating platform engineering variations into criteria relevant to mainstream IT.
    Intel hopes to get some traction with a feature that AMD lacks, an integrated power microcontroller. AMD had no specific observations to offer on a feature that Intel kept secret until a couple of weeks ago. On servers, AMD believes that power conservation is done most effectively at the wall: If a server isn't working hard enough, turn it off. That's my line, but it's a long slog to get IT to take up this idea. In the meantime, servers should be at least as clever as desktops at using less energy when they have less work to do.
    I understand that AMD is frustrated by the very roadblock I've called out: No matter how ingenious chip engineers are, if Microsoft doesn't pick a feature up, it's as good as wasted effort. This is especially true of power management. If server BIOSes and Windows Server OSes don't leverage Intel's power management microcontroller any better than they do quad-core Opteron's designed-in efficiencies, then Intel's bragging point will be lost on all but notebook users. If Intel has enough sway to make Microsoft twiddle Nehalem's power knobs and dials, or better still, let the microcontroller manage them itself, then Microsoft will have to answer for failing to invest as much care in exploiting architectural and platform features unique to quad-core Opteron.
    Intel did more than catch up in cache design for the Nehalem architecture. The huge, shared Level 2 cache has given way to a much smaller Level 2 cache dedicated to each core. Like AMD (and like some previous Intel Xeon designs), Nehalem adopts a three-level cache. Intel uses the Level 3 cache to implement cache probe filtering, a technique that cuts down on core-to-core bus traffic. The handling of cache is a major and palpable differentiator between CPU architectures, especially as other engineering gaps tighten. There is a lot of room for innovation here.
    Intel makes marketing hay with the sort of esoteric innovations that grab my attention, but which AMD asserts won't be felt on the server side. One such feature is HyperThreading (HT). This Netburst feature got the axe when Intel went to Core. I always considered HT one of Intel's bolder engineering moves, and now we'll see how it fares in a modern setting.
    AMD is betting that instead of pulling up to a 30% increase in performance with ideally-tuned workloads, HT will bring single-digit boosts. In AMD's view, HT came about as a means of giving the chip something to do while it was waiting for memory. Now that on-chip controllers and faster RAM knock memory latency down to a fraction of what it was in Pentium 4 heyday, there isn't that much waiting time to fill. I have higher expectations in the long run. I think that multithreading will become the smartest way to squeeze more performance out of a socket, especially as programmers and compilers get smarter about parallelisation of code.
    AMD considers it unlikely that server applications will feel other Nehalem platform and architecture enhancements, such as Version 4.2 of the Streaming SIMD Extensions (SSE) and Intel's Application-Targeted Accelerators. Both require recoding, perhaps hand-coding to put to use. I see tremendous potential benefit, but it's only reachable where developers are willing to risk incompatibility with other types of systems.
    There's the rub. At the platform level, Nehalem's advances will be felt by IT without requiring any change in software. To feel Nehalem's power management and architectural (CPU) performance tweaks requires new code. That's effort that high-performance computing and specialised verticals like medical imaging will shoulder, but as a rule, major ISVs shy away from forking code to bring advantages to a small fraction of the x86 server installed base. And as much as I enjoy handwritten in-line assembly code, it's not your average in-house coder's cup of tea.
    AMD hopes to call attention to the fact that Nehalem requires new servers. AMD's message is one of platform longevity. Between serious platform revisions, AMD lets customers and OEMs do system upgrades with CPU swaps and BIOS updates. AMD's OEMs aren't consistent in enabling this — I don't know how many IBM server customers were able to get dual-core to quad-core Opteron chip upgrades. Longevity should matter a great deal as budgets tighten. If Intel feels it finally has a platform with some headroom to it, it might relax the projected expectation of full system replacement every two years.
    Since AMD had the floor to itself, it couldn't resist taking one last shot. Now that Intel has shed much of its legacy system platform, it faces a legacy core architecture. Nehalem is still a modified Pentium III core. During the time that Intel has spent cleaning up its platform, AMD, whose server platform has neither had nor needed overhauling since gen-one Opteron, has been working on CPU architectures. Its most anticipated project is Fusion, a CPU that brings AMD's microprocessor, embedded, chipset and GPU chops, along with some time-proven big iron ideals, to bear on a single socket. Until AMD can blow Intel away again, it's comfortable with a share of the x86 server market.
    The fact that Intel's platform has caught up to AMD's doesn't automatically put AMD at a disadvantage. What it does is level the field, which breeds aggressive innovation and pricing as close competitors fight to differentiate their products. Apples to apples in x86 servers is good for IT.

  • More Intel chips

    Intel has announced four new quad-core Xeon models that use a halogen-free packaging technology.

  • Microcontroller steals the show at IDF

    Intel Developer Forum has wrapped up, and there's no question that Nehalem owned the show. Intel's engineering crew was practically beside itself; finally, it had something new to say to software and hardware developers. It was hard to tell whether the phrase "most significant update to Intel's x86 in ten years", uttered often by Intel staff, carried a tinge of frustration, but Nehalem's specs elevate that mantra from marketing to reality.
    When Intel opened its raincoat recently to reveal Nehalem's secret weapon — an on-package power management microcontroller — I shouted "that's what I'm talking about!". That's the way to bring more than lip service to green IT, guys, and sooner than most observers (myself included) expected. Sign me up for three-level cache architecture, hyperthreading and direct virtual machine links to physical peripherals, but if Nehalem's power management delivers its potential, and if Microsoft and Intel server OEMs exploit the technology, I'm open to declaring a new ball game in x86 servers.
    Modern x86 CPUs are pretty stupid by mainframe standards. We got so caught up in making microprocessors fast, small and cheap that we scooped out the qualities that have defined server systems since we referred to IT as Data Processing. AMD, with its close relationship with IBM, looked on track to make x86 server CPUs serious machinery — self-monitoring, self-healing, self-reporting, made of multiple autonomous units that can be dispatched to specialised tasks without interrupting the flow of common work. I never expected that Intel would beat AMD to it, but if AMD had done Nehalem, I'd judge it a functional early pass at elements of the mainframe-inspired server CPU design laid out by AMD's CTO two years ago.
    Intel baked a small sample of task-specific autonomy into Nehalem with a couple of small, highly specialised instruction units that I see as flagbearers, a preview of what Intel is able to add to future x86 CPUs in microcode or through some similarly simple mechanism. But the more impressive accomplishment is Nehalem's incorporation of a power management microcontroller. Intel claims that this will monitor temperature, power utilisation and workload, and apportion that workload among as few processor cores as are needed to do the job. Cores that would ordinarily divvy up mundane threads that could be executed more efficiently by a single core aren't merely idled, they're powered down. At least that's the pitch. Intel is a bit coy with the details, except to say that in transistor count, Nehalem's power controller is similar in complexity to an 80486 CPU. The message there is that Nehalem's power controller really is an autonomous unit, and Intel's use of the term "microcontroller" signals to me that it is externally programmable. I'll be disappointed if reality doesn't match the message.
    The detail that Intel hasn't addressed relates to operational ownership of this microcontroller, and that's a particularly sticky point for me. As processors become more malleable, who gets to shape them, and who gets to shut the door to further changes? BIOS? Boot loader? Kernel? Device driver? I've addressed the opaque, proprietary control that independent BIOS vendors, system OEMs, and Microsoft exert over processor and device registers that have a dramatic impact on performance. Nehalem's power controller has similar reach with regard to power utilisation and scheduling.
    To be blunt, it's a resource that Microsoft will want to own, or reserve the right to disown by overriding the power controller's settings with Windows' more primitive run-time controls. This is already seen in AMD Barcelona servers running Windows Server 2008. Left to itself, Barcelona can manage bus and core power beautifully without Windows lifting a finger. That's core to the CPU's design. Yet Windows can ignore BIOS and user-defined power settings, and there's no checkbox to disable Windows' power state manipulation.
    There should be. By putting a microcontroller in charge, Intel's gotten the best kind of religion with regard to power control. Nehalem reads like a CPU with a built-in greenness dial. But you'll never feel it if BIOS and the OS lock it down, and if Intel doesn't provide developers and users with the means to grab control at run-time. If I want to run my server on one core over the weekend, I should be able to do that.
    One thing that a microcontroller could be trained to do is hoodwink the OS into believing that it has control over the system's power state while the power controller does what it, or a savvy system owner, knows is best. Nehalem's power management controller is Intel's engineering secret weapon and a welcome advance in x86 technology. Let's just hope that Intel keeps it open so that it doesn't fall into the wrong hands.

  • Intel to release six-core chip this month

    The quad-core chips that have sat atop the microprocessor heap for the past two years are about to start being replaced by bigger, burlier six-core processor technology.

  • Intel SSD goes smaller

    Intel has launched a much smaller version of its Z-P230 SSD (solid-state drive) aimed at netbooks and mini-desktops.

  • FryUp: Microsoft Photosynthed

    — Microsoft Photosynthed
    — Ebay auctions going, going…
    — Intesla
    — Streaming pile of net neutrality

  • New Intel processor targets consumer and mobile markets

    Intel has launched its System-on-Chip (SoC) EP8579 integrated processor, which it says offers lower power and customisation capabilities for embedded voice, storage and security applications. The new product family is the first wave of Intel's revamped SoC design, which adds smarter chip intelligence, according to the company.

  • New AMD chip

    AMD is developing a low-power processor for mobile devices and sub-notebooks, quashing speculation that it had abandoned the project. The chip will compete with Intel's Atom processor.

  • Mobile quad-core chip

    Intel will release its first quad-core processor for laptops next month. The chip will carry Intel's Core 2 Extreme label.

  • Intel lays down challenge to mobile chipmakers

    Despite a slow entry into the market, Intel's mobile chips may dominate the space in the long run by offering value and software compatibility that competitors like Arm will find tough to match, according to Intel digital enterprise group co-general manager and senior vice president Pat Gelsinger.

  • Intel to offer free spec

    Intel plans to make the specification for a USB 3.0 host controller freely available during the second half of this year, hitting back at rumors it wanted to keep the technology for itself.

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